1. Field
Example embodiments relate to an apparatus for measuring a transmission delay of a transmission path in a semiconductor device by using a replicate transmission path having the same structure as that of the transmission path whose transmission delay is to be measured.
2. Description of Related Art
When developing a semiconductor device, it is important to consider the aim of the design of the semiconductor device. For example, the timing margin of a signal transmission path in a semiconductor device is an important factor in determining the operating speed of the device and is also important in terms of yield.
An actual transmission delay time, during which signal transmission via a transmission path is delayed due to various factors (e.g., a variety of components existing on the transmission path and the resistance and capacitance of wires), is different from the delay time obtained by a simulation. When components are scaled down during a semiconductor manufacturing process, the timing change within the device accordingly increases. Thus, in order to increase productivity, a designer needs to ascertain the actual timing value (e.g., a transmission delay) of the desired circuitry of each of the implemented chips.
FIG. 1 is a block diagram illustrating a transmission delay. Referring to FIG. 1, a semiconductor chip includes an input terminal 130 in which a signal transmitted from another circuit existing outside or inside the semiconductor chip is received as an input signal, a transmission path 110 in which the input signal is transmitted, and an output terminal 150 in which the transmitted input signal is output as an output signal.
In order to measure the transmission delay of the transmission path 110, the time ranging from when the input signal is input to the transmission path 110 to when the output signal is output from the transmission path 110 is measured. However, it is difficult to precisely measure the actual time between when the input signal is input to the transmission path 110 and when the output signal is output from the transmission path 110.
In conventional methods, when transmission circuits whose transmission delays are to be measured are apart from each other within the chip, an error may be generated due to the delay generated in the interconnection line when making a closed loop. Furthermore, a sum of the time during which the logic level of a signal input to a transmission circuit transitions from a low level to a high level and a time during which the logic level of the signal transitions from a high level to a low level may be measured. As such, there remains a demand for a system that may more accurately measure the delay by removing the interconnection line parasitically generated when making a closed loop and that may separately measure a time during which the logic level of a signal input to the transmission circuit transitions from a lower level to a high level and a time during which the logic level of the signal transitions from a high level to a low level.